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N02L63W3A
2Mb Ultra-Low Power Asynchronous CMOS SRAM
128K x 16bit Overview
The N02L63W3A is an integrated memory device containing a 2 Mbit Static Random Access Memory organized as 131,072 words by 16 bits. The device is designed and fabricated using ON Semiconductor's advanced CMOS technology to provide both high-speed performance and ultra-low power. The device operates with a single chip enable (CE) control and output enable (OE) to allow for easy memory expansion. Byte controls (UB and LB) allow the upper and lower bytes to be accessed independently. The N02L63W3A is optimal for various applications where low-power is critical such as battery backup and hand-held devices. The device can operate over a very wide temperature range of -40oC to +85oC and is available in JEDEC standard packages compatible with other standard 128Kb x 16 SRAMs.
Features
* Single Wide Power Supply Range 2.3 to 3.6 Volts * Very low standby current 2.0A at 3.0V (Typical) * Very low operating current 2.0mA at 3.0V and 1s (Typical) * Very low Page Mode operating current 0.8mA at 3.0V and 1s (Typical) * Simple memory control Single Chip Enable (CE) Byte control for independent byte operation Output Enable (OE) for memory expansion * Low voltage data retention Vcc = 1.8V * Very fast output enable access time 30ns OE access time * Automatic power down to standby mode * TTL compatible three-state output driver * Compact space saving BGA package available
Product Family
Part Number N02L63W3AB N02L63W3AT N02L63W3AB2 N02L63W3AT2 Package Type 48 - BGA 44 - TSOP II 48 - BGA Green 44 - TSOP II Green 55ns @ 2.7V -40oC to +85oC 2.3V - 3.6V 70ns @ 2.3V 2 A 2 mA @ 1MHz Operating Temperature Power Supply (Vcc) Speed Standby Operating Current (ISB), Current (Icc), Typical Typical
(c)2008 SCILLC. All rights reserved. July 2008 - Rev. 15
Publication Order Number: N02L63W3A/D
N02L63W3A
Pin Configurations
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIN ONE 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
1 A B C D E F G H
LB I/O8 I/O9 VSS VCC
2
OE UB I/O10 I/O11 I/O12
3
A0 A3 A5 NC NC A14 A12 A9
4
A1 A4 A6 A7 A16 A15 A13 A10
5
A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
6
NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC
N02L63W3A TSOP
I/O14 I/O13 I/O15 NC NC A8
48 Pin BGA (top) 6 x 8 mm
Pin Descriptions
Pin Name A0-A16 WE CE OE LB UB I/O0-I/O15 NC VCC VSS Pin Function Address Inputs Write Enable Input Chip Enable Input Output Enable Input Lower Byte Enable Input Upper Byte Enable Input Data Inputs/Outputs Not Connected Power Ground
Rev. 15 | Page 2 of 11 | www.onsemi.com
N02L63W3A
Functional Block Diagram
Address Inputs A0 - A3
Word Address Decode Logic
Address Inputs A4 - A16
Page Address Decode Logic
32K Page x 16 word x 16 bit RAM Array
Input/ Output Mux and Buffers
Word Mux
I/O0 - I/O7
I/O8 - I/O15 CE WE OE UB LB
Control Logic
Functional Description
CE H L L L L WE X X L H H OE X X X3 L H UB X H L
1
LB X H L
1
I/O0 - I/O151 High Z High Z Data In Data Out High Z
MODE Standby2 Active Write3 Read Active
POWER Standby Active Active Active Active
L1 X
L1 X
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. 2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance1
Item Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN = 0V, f = 1 MHz, TA = 25oC Min Max 8 8 Unit pF pF
VIN = 0V, f = 1 MHz, TA = 25oC
1. These parameters are verified in device characterization and are not 100% tested
Rev. 15 | Page 3 of 11 | www.onsemi.com
N02L63W3A
Absolute Maximum Ratings1
Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time Symbol VIN,OUT VCC PD TSTG TA TSOLDER Rating -0.3 to VCC+0.3 -0.3 to 4.5 500 -40 to 125 -40 to +85 260oC, 10sec Unit V V mW
oC oC oC
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Item Supply Voltage Data Retention Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current @ 1 s Cycle Time2 Read/Write Operating Supply Current @ 70 ns Cycle Time2 Page Mode Operating Supply Current @ 70ns Cycle Time2 (Refer to Power Savings with Page Mode Operation diagram) Read/Write Quiescent Operating Supply Current3 Symbol VCC VDR VIH VIL VOH VOL ILI ILO ICC1 ICC2 IOH = 0.2mA IOL = -0.2mA VIN = 0 to VCC OE = VIH or Chip Disabled VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0, f=0 VIN = VCC or 0V Chip Disabled tA= 85oC, VCC = 3.6 V VCC = 1.8V, VIN = VCC or 0 Chip Disabled, tA= 85oC 2.0 2.0 12 Chip Disabled2 Test Conditions Min. 2.3 1.8 1.8 -0.3 VCC-0.2 0.2 0.5 0.5 4.0 16.0 VCC+0.3 0.6 Typ1 Max 3.6 Unit V V V V V V A A mA mA
ICC3
4
mA
ICC4
3.0
mA
Maximum Standby
Current3
ISB1
20
A
Maximum Data Retention Current3
IDR
10
A
1. Typical values are measured at Vcc=Vcc Typ., TA=25C and are not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 3. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS
Rev. 15 | Page 4 of 11 | www.onsemi.com
N02L63W3A
Power Savings with Page Mode Operation (WE = VIH)
Page Address (A4 - A16 )
Open page ...
Word Address (A0 - A3)
Word 1
Word 2
Word 16
CE
OE LB, UB
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power saving feature. The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power SRAMs.
Rev. 15 | Page 5 of 11 | www.onsemi.com
N02L63W3A
Timing Test Conditions
Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Operating Temperature 0.1VCC to 0.9 VCC 5ns 0.5 VCC CL = 30pF -40 to +85 oC
Timing
Item Read Cycle Time Address Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z output Output Enable to Low-Z Output Byte Select to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Byte Select Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Byte Select to End of Write Write Pulse Width Address Setup Time Write Recovery Time Write to High-Z Output Data to Write Time Overlap Data Hold from Write Time End Write to Low-Z Output Symbol tRC tAA tCO tOE tLB, tUB tLZ tOLZ tLBZ, tUBZ tHZ tOHZ tLBHZ, tUBHZ tOH tWC tCW tAW tLBW, tUBW tWP tAS tWR tWHZ tDW tDH tOW 40 0 10 10 5 10 0 0 0 10 70 50 50 50 40 0 0 20 35 0 10 20 20 20 2.3 - 3.6 V Min. 70 70 70 35 35 10 5 10 0 0 0 10 55 40 40 40 40 0 0 20 20 20 20 Max. 2.7 - 3.6 V Min. 55 55 55 30 30 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Rev. 15 | Page 6 of 11 | www.onsemi.com
N02L63W3A
Timing of Read Cycle (CE = OE = VIL, WE = VIH)
tRC Address tAA tOH
Data Out
Previous Data Valid
Data Valid
Timing Waveform of Read Cycle (WE= VIH)
tRC Address
tAA tCO
tHZ
CE
tLZ tOE
tOHZ
OE tOLZ tLB, tUB LB, UB tLBLZ, tUBLZ Data Out High-Z tLBHZ, tUBHZ Data Valid
Rev. 15 | Page 7 of 11 | www.onsemi.com
N02L63W3A
Timing Waveform of Write Cycle (WE control)
tWC Address tAW tCW CE tLBW, tUBW LB, UB tAS WE tDW High-Z Data In tWHZ Data Out High-Z tDH tWP tWR
Data Valid tOW
Timing Waveform of Write Cycle (CE Control)
tWC Address tAW CE tAS tLBW, tUBW LB, UB tWP WE tDW Data In tLZ Data Out tWHZ tDH tCW tWR
Data Valid
High-Z
Rev. 15 | Page 8 of 11 | www.onsemi.com
N02L63W3A
44-Lead TSOP II Package (T44)
18.410.13
10.160.13
11.760.20
0.80mm REF
0.45 0.30
SEE DETAIL B
DETAIL B
1.100.15
0o-8o 0.20 0.00 0.80mm REF
Note: 1. All dimensions in inches (Millimeters) 2. Package dimensions exclude molding flash
Rev. 15 | Page 9 of 11 | www.onsemi.com
N02L63W3A
Ball Grid Array Package
A1 BALL PAD CORNER (3) D 0.280.05 1.240.10 1. 0.350.05 DIA. E 2. SEATING PLANE - Z 0.15 Z 0.05 TOP VIEW SIDE VIEW 1. DIMENSION IS MEASURED AT THE A1 BALL PAD MAXIMUM SOLDER BALL DIAMETER. CORNER PARALLEL TO PRIMARY Z. 2. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. A1 BALL PAD CORNER I.D. TO BE MARKED BY INK. K TYP J TYP e Z
SD
e SE
BOTTOM VIEW
Dimensions (mm)
e = 0.75 D 60.10 E SD 80.10 0.375 SE 0.375 J 1.125 K 1.375 BALL MATRIX TYPE FULL
Rev. 15 | Page 10 of 11 | www.onsemi.com
N02L63W3A
Ordering Information
Part Number N02L63W3AT5I N02L63W2AT25I N02L63W3AB5I N02L63W3AB25I N02L63W3AT5IT N02L63W3AT25IT N02L63W3AB5IT N02L63W3AB25IT Package Leaded 44-TSOP II Green 44-TSOP II (RoHS Compliant) Leaded 48-BGA Green 48-BGA (RoHS Compliant) Leaded 44-TSOP II Green 44-TSOP II (RoHS Compliant) Leaded 48-BGA Green 48-BGA (RoHS Compliant) Shipping Method Tray Tray Tray Tray Tape & Reel Tape & Reel Tape & Reel Tape & Reel
Revision History
Revision #
A B C D E F G H I J K L M N 15
Date
Dec. 1999 Sept. 2000 Oct. 2000 Oct. 2000 Jan. 2001 Mar. 2001 May 2001 June 2001 Sept. 2001 Dec. 2001 Nov. 2002 Oct. 2004 Nov. 2005 September 2006 July 2008 Initial Preliminary Release
Change Description
Modified Voltage Range and Standby Current Limits. Added Missing Tas Parameter Specification. Modified Standby Current Specifications. Extensive Modification to use voltage regulator design Modified BGA pinout, access time 70ns @ 2.7V, misc. errata Changed access time to 55ns, modified 44-Lead TSOP Package diagram Revised voltage range in Timing table, revised Dimensions table Minor parametric modifications, full production release Part number change from EM128L16, modified Overview and Features, added Page Mode Operation diagram, revised Operating Characteristics table, Package diagram, Functional Description table and Ordering Information diagram Replaced Isb and Icc on Product Family table with typical values Added Pb-Free and Green Package Option Removed Pb-Free Pkg, added Green Pkg and RoHS Compliant Converted to AMI Semiconductor Converted to ON Semiconductor and new part numbers
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor PO Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East & Africa Technical Support: Phone 421-33-790-2910 Japan Customer Focus Center: Phone 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
Rev. 15 | Page 11 of 11 | www.onsemi.com

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